Silicon: The World's Most Strategic Commodity

How semiconductors became the new oil — from the transistor to TSMC, from export controls to orbital data centers. A complete guide for investors and the curious.

1. Executive Summary

For most of the 20th century, the commodity that defined geopolitical power was oil. Wars were fought over it. Currencies were pegged to it. Empires rose and fell with its price. In 2026, that role has been taken by something far smaller and far stranger: patterns of atoms etched onto thin discs of silicon.

A modern smartphone contains chips with transistors smaller than a single virus particle. A high-end GPU trained on the latest manufacturing process packs more than 200 billion transistors into a piece of silicon roughly the size of a postage stamp. The single machine that makes those features possible — ASML's High-NA EUV lithography scanner — costs roughly $380 million, weighs over 200 tonnes, and requires three Boeing 747 freighters and 40 trucks to ship.

One country, Taiwan, manufactures more than 90% of the world's leading-edge logic chips. One company, ASML, holds a global monopoly on the lithography tools required to make them. One company, NVIDIA, designs more than 80% of the GPUs being installed in AI data centers. Three companies — Samsung, SK Hynix, and Micron — produce essentially all of the high-bandwidth memory stacked next to those GPUs. Every single one of these chokepoints sits inside a tightening US–China geopolitical contest.

This article is a complete tour of that landscape: how a chip is actually made, how the industry is organized, why the supply chain crosses ~25 countries before a single phone is sold, how US export controls and the CHIPS Act are redrawing the map, and where the trillion-dollar AI capex cycle leads — including the most underappreciated frontier of all: silicon in orbit. By the time you finish, you will understand semiconductors better than most people who own the stocks.

2. Genesis: How a Chip Actually Works

Before you can think clearly about TSMC, NVIDIA, or export controls, you need a working mental model of what a chip is. The good news: the core idea is genuinely simple. The complexity comes from doing it 200 billion times on a piece of silicon the size of a fingernail.

2.1 The Transistor: A Switch the Size of a Virus

A modern processor is, at its heart, an enormous collection of microscopic switches called transistors. Each transistor has three terminals: a source, a drain, and a gate. Apply a voltage to the gate, and current flows from source to drain — the switch is “on” (a binary 1). Remove the voltage, no current flows — “off” (a 0). String billions of these switches together with copper wires and you can implement any logical operation: addition, multiplication, branching, memory.

2.2 From Sand to Wafer

Silicon itself starts as ordinary sand — silicon dioxide. It is purified to 99.9999999% silicon (“nine nines”), melted, and pulled into a single cylindrical crystal (an “ingot”) using the Czochralski process. That ingot is sliced into wafers — thin discs typically 300 millimetres in diameter — that are polished to a mirror finish flat to within a few atoms across their surface. These wafers are the canvas on which every chip is painted.

The wafer industry itself is a chokepoint most investors never see. Two Japanese companies — Shin-Etsu Chemical and SUMCO — supply more than half of the world's 300mm wafers. A shortage of polished wafers in 2021 contributed to the auto industry chip crisis as severely as the foundry shortage did.

2.3 Lithography: Painting With Light

Once you have a polished wafer, the magic begins. Lithography is the process of projecting a circuit pattern onto the wafer, coating it in chemicals that respond to that pattern, and etching the resulting design into the silicon. This is repeated dozens of times — modern chips require 80 to 100+ separate lithography layers, each precisely aligned to the previous one.

The shorter the wavelength of light, the smaller the features you can print. For decades, the industry used deep ultraviolet (DUV) light at 193nm wavelengths. To go smaller, ASML had to invent something extraordinary: extreme ultraviolet light at 13.5nm. The process to generate it is borderline absurd. Inside the EUV machine, a tin droplet 30 microns wide is shot into a vacuum chamber. A 25-kilowatt CO2 laser hits it twice — once to flatten it, once to vaporize it into plasma — and that plasma emits the EUV light. This happens 50,000 times per second. The light then bounces off a series of mirrors so flat that, if scaled up to the size of Germany, the tallest bump would be a fraction of a millimetre.

2.4 What “3 Nanometres” Actually Means (And Does Not)

When TSMC, Samsung, or Intel announce a new “3nm” or “2nm” process, it is tempting to believe those numbers describe a physical dimension on the chip. They no longer do. Around the 22nm node, “nanometre” became a marketing label rather than a measurement. A modern 3nm transistor's actual smallest feature is closer to 20nm. The number now describes a generation — a performance and density tier — not a length.

The reason the industry kept the naming convention is competitive. Moving from one node to the next typically delivers ~15% performance, ~30% power, or ~70% area improvement. Every node is harder, slower, and more expensive than the last. A modern leading-edge fab costs $20–30 billion to build, requires roughly 7,000 specialist engineers to operate, and consumes more electricity than a small city.

3. The Stack: Design, Fab, Tools, OSAT

Unlike oil — where a single major company explores, extracts, refines, and distributes — the semiconductor industry is brutally specialized. Every chip you have ever used is the product of a global division of labour so deep that no single country, and no single company, can replicate it. Understanding this stack is the key to understanding everything that follows.

3.1 Fabless: The Designers

Fabless companies design chips but own no factories. NVIDIA, AMD, Apple, Qualcomm, Broadcom, and MediaTek are the giants of this layer. They employ thousands of engineers, license intellectual property (IP) from firms like Arm, and use electronic design automation (EDA) software from Synopsys and Cadence to translate transistor-level logic into a set of geometric patterns — the “mask set” — that a foundry can manufacture.

The fabless model exploded after TSMC pioneered the pure-play foundry in 1987. Suddenly, a startup with great architecture and no capital for a factory could compete with vertically integrated giants like Intel. Today, fabless companies capture some of the highest margins in the entire technology stack — NVIDIA's gross margins have run above 70% during peak AI demand — because their cost base is essentially intellectual.

3.2 Foundries: The Manufacturers

A foundry takes a customer's mask set and turns it into wafers full of chips. TSMC is the dominant force, manufacturing roughly 60% of all foundry revenue globally and the overwhelming majority of leading-edge logic. Samsung Foundry, Intel Foundry, SMIC (China), and GlobalFoundries fill out the rest. Of those, only TSMC, Samsung, and Intel are currently capable of producing leading-edge nodes (3nm and below).

3.3 IDMs: The Vertically Integrated

Integrated Device Manufacturers (IDMs) design and manufacture their own chips. Intel is the iconic Western IDM. Samsung is an IDM in both logic and memory. Micron and SK Hynix are IDMs focused on memory. For most of computing history, IDMs ruled — until the fabless/foundry model began stripping them apart. Intel's ongoing struggle to compete with TSMC is the most consequential corporate story of the past decade.

3.4 OSAT and Advanced Packaging

Once chips are manufactured on a wafer, they need to be cut apart (“diced”), tested, and packaged into the form that gets soldered onto a circuit board. This work is done by OSAT companies — Outsourced Semiconductor Assembly and Test. The largest are ASE Technology (Taiwan), Amkor (US), JCET (China), and SPIL (now part of ASE).

For years, packaging was an afterthought. In 2026, it is one of the most important chokepoints in the entire industry. The reason is something called CoWoS — Chip-on-Wafer-on-Substrate. Advanced AI chips like NVIDIA's Blackwell are no longer single dies. They are multiple chiplets — GPU compute, stacks of HBM, I/O — assembled together on a silicon interposer. CoWoS capacity, not foundry capacity, has been the binding constraint for NVIDIA throughout 2024–2025.

4. The Global Supply Chain

The semiconductor supply chain is the most geographically concentrated, most interdependent system in the global economy. There is no industry — not oil, not aerospace, not pharmaceuticals — that depends on so few places for so much. Here is how it actually lays out across the map.

4.1 Taiwan: The Beating Heart

Taiwan is the world's indispensable nation for advanced logic. TSMC alone accounts for more than 90% of leading-edge logic manufacturing. Its fab clusters in Hsinchu, Tainan, and Taichung produce the silicon that powers every iPhone, every NVIDIA AI GPU, every AMD server CPU, and most of the rest of the modern compute economy. A serious disruption to Taiwan — military, seismic, or grid-based — would not be a recession event. It would be a global depression event.

Taiwanese officials have referred to this concentration as a “silicon shield” — the idea that the world cannot afford to let Taiwan be attacked. Strategists in Beijing and Washington increasingly view it the opposite way: as a vulnerability that must be dispersed.

4.2 South Korea: The Memory Empire

South Korea's Samsung and SK Hynix dominate the memory market. DRAM (used as a computer's main working memory) and NAND (used for storage) are essentially a two-country oligopoly: South Korea and the United States (Micron, in Idaho). HBM — the stacked DRAM that sits beside every AI GPU — is currently led by SK Hynix, which became NVIDIA's preferred HBM3E supplier and one of the most important companies in the entire AI stack.

4.3 Japan: The Hidden Materials Power

Japan does not dominate any single high-profile layer of the stack — but it dominates many of the materials layers underneath it. Roughly 90% of high-end photoresist (the light-sensitive chemical used in lithography) is Japanese. Shin-Etsu and SUMCO together supply more than half of the world's 300mm wafers. Tokyo Electron is one of the four big equipment makers globally. When Japan restricted exports of three chemicals to South Korea in 2019, it caused a temporary panic that demonstrated how thin the materials margin really is.

4.4 The Netherlands: The ASML Singleton

Veldhoven, a small Dutch town near Eindhoven, hosts the headquarters and primary manufacturing campus of ASML — the only company in the world capable of producing EUV lithography systems. There is no second source. There is no plausible second source on a horizon of less than a decade. Without ASML, the leading edge of semiconductor progress does not exist. The Dutch government, under heavy US pressure, now controls who is allowed to buy ASML's most advanced machines.

4.5 The United States: Design, IP, and the CHIPS Revival

The US no longer manufactures the majority of leading-edge chips, but it dominates the layers with the highest margins: chip design (NVIDIA, AMD, Apple, Qualcomm, Broadcom), EDA software (Synopsys, Cadence, Siemens), processor IP (parts of Arm, RISC-V foundations), and some critical equipment (Applied Materials, LAM Research, KLA). The CHIPS and Science Act of 2022, with roughly $39 billion in direct manufacturing subsidies, is now funding new fabs from Intel in Arizona and Ohio, TSMC in Arizona, Samsung in Texas, and Micron in New York. These will not break Taiwan's leading-edge dominance this decade, but they begin the slow process of rebuilding domestic capacity.

4.6 China: The Other Pole

China is the world's largest consumer of semiconductors and, simultaneously, the country furthest behind in producing the most advanced ones. SMIC, China's leading foundry, is operating roughly two to three nodes behind TSMC. Huawei's 2023 Mate 60 phone, which contained a 7nm-class chip from SMIC, was treated by US policymakers as evidence that export controls were not working as intended. The subsequent tightening of controls in 2023, 2024, and 2025 has been steadily aimed at preventing China from acquiring EUV and the most advanced DUV tools needed to push further.

5. Trade & Geopolitics: The Silicon Cold War

Until 2018, semiconductors were largely treated as a commercial sector. Since then, every major economy has reclassified them as a strategic asset on the level of weapons systems. The result has been the fastest reordering of an industrial supply chain in modern history — and one of the most important investment themes of the decade.

5.1 The CHIPS Act and the Subsidy Race

The CHIPS and Science Act of August 2022 authorized roughly $52 billion in US funding to revive domestic semiconductor manufacturing, of which about $39 billion is direct manufacturing subsidy. The EU followed with its own Chips Act (€43 billion). Japan, South Korea, China, India, and Singapore have all introduced their own programs. The cumulative announced public subsidy globally now exceeds $300 billion — the largest peacetime industrial policy push since the post-war reconstruction of Europe and Japan.

5.2 Export Controls: The Sharper Weapon

The October 7, 2022 export controls, expanded in October 2023 and December 2024, are arguably the most important economic action of the decade. The US Commerce Department's Bureau of Industry and Security (BIS) effectively cut off China's access to:

Crucially, the rules are extraterritorial: any foreign-produced chip that contains US-origin technology can be subject to US export controls. This is why ASML, a Dutch company, must seek Dutch government licenses (which are coordinated with Washington) to ship High-NA EUV machines.

5.3 China's Response

Beijing's response has been a multi-decade industrial policy push, including the Big Fund (now totalling more than $100 billion across three tranches), aggressive subsidies to SMIC, YMTC, CXMT, and Huawei's HiSilicon. The strategic emphasis has shifted toward two areas: (a) catching up on legacy and mature nodes — where China is now adding capacity at a pace that may flood the global market with cheap 28nm and 14nm wafers, pressuring incumbents like GlobalFoundries and UMC; and (b) building a parallel, domestically controllable supply chain in everything from EDA to lithography. A genuine indigenous EUV competitor is still many years away, but DUV-based workarounds are improving.

5.4 Taiwan: The Tail Risk That Anchors Everything

There is no analysis of semiconductors in 2026 that can responsibly ignore Taiwan. Most credible analysts assign a low-but-not-negligible probability to a military scenario before 2030. The economic case for global participation in defending — or at minimum, deterring an action against — Taiwan rests almost entirely on TSMC. The CHIPS Act, Japan's Rapidus subsidies, the EU Chips Act, and the steady diversification of advanced packaging into Arizona, Japan, and Germany are all attempts to slowly reduce the asymmetric dependence on a single island.

6. The Money: The AI Capex Cycle

For most of the last decade, the semiconductor industry traded on smartphone cycles, PC cycles, and the cyclicality of memory. Since the launch of ChatGPT in November 2022, all of that has been overshadowed by a single phenomenon: the AI capex super-cycle. Understanding the scale and structure of this spend is essential for understanding why NVIDIA briefly became the most valuable company on Earth in 2024 — and why the bull case and bear case both rest on the same set of numbers.

6.1 Hyperscaler Capex

The four US hyperscalers — Microsoft, Alphabet, Meta, and Amazon — together guided to roughly $325 billion of capital expenditure in 2025, the majority of it directed at AI-related infrastructure: GPUs, custom AI accelerators (TPUs, Trainium, MTIA), networking, power, cooling, and buildings. That figure was approximately $230 billion in 2024 and is on track to exceed $400 billion in 2026 if current guidance holds. The cumulative four-year spend approaches a trillion dollars.

Add in Oracle, CoreWeave, sovereign AI projects (UAE's G42, Saudi Arabia's HUMAIN, France's sovereign initiatives), and a second tier of large enterprises, and the global AI capex pipeline is genuinely without modern precedent — comparable in scale to the buildout of the Interstate Highway System or the early 2000s telecom fiber boom.

6.2 NVIDIA's Position and Its Mirror Risk

NVIDIA has captured an estimated 80–90% of the AI training GPU market and a slightly smaller but still dominant share of inference. Its data center revenue grew from roughly $15 billion in fiscal 2023 to more than $115 billion in fiscal 2025. Gross margins peaked above 75%. By any historical standard, this is one of the most extraordinary business inflections in corporate history.

The mirror image of that growth is concentration risk. NVIDIA's top four customers — the hyperscalers — account for roughly half of its data center revenue. If any combination of them cuts capex sharply, the impact is immediate. The bull case is that AI demand keeps outpacing supply through at least 2027 and that NVIDIA's software moat (CUDA) prevents customers from migrating to in-house silicon at scale. The bear case is that custom silicon — Google's TPU v6/v7, Amazon's Trainium 2, Microsoft's Maia 100/200 — quietly eats into the same workloads at meaningfully better unit economics.

6.3 TSMC and ASML: The Picks-and-Shovels

Behind every AI GPU sold is a TSMC wafer. Behind every TSMC wafer is an ASML scanner. These two companies — together with the broader equipment ecosystem of Applied Materials, LAM Research, KLA, and Tokyo Electron — are the picks-and-shovels of the AI gold rush, and they capture economics that do not depend on any single fabless winner. Whether NVIDIA, AMD, or a Google in-house design ultimately wins the GPU war, TSMC manufactures most of them, and ASML supplies the lithography tools.

6.4 The Memory Tag-Along

Every NVIDIA GPU shipped sits next to multiple stacks of high-bandwidth memory. A single Blackwell B200 module uses up to 192 GB of HBM3E across eight stacks. The result has been the most dramatic transformation of the memory industry in 20 years: SK Hynix, Samsung, and Micron — historically commoditized cyclical names — are now strategic suppliers with multi-year visibility, sold-out capacity, and pricing power. Memory cyclicality has not been abolished, but the trough-to-peak amplitude of the cycle has narrowed materially.

7. Why It Is All Interconnected

Take any single semiconductor in your life — the application processor in your phone, the controller in your earbuds, the GPU in your laptop — and trace its supply chain. The result is almost comically global. Here is what a typical smartphone SoC actually looks like, from atoms to pocket.

That is roughly 25 countries touched before a single phone is sold — and the count rises sharply if you include sub-suppliers (specialty gases, sputter targets, exotic dopants). There is no industrial process on the planet more globalised. The implication: a disruption in any one node — a fire at a Japanese chemical plant, an export control change in Washington, an earthquake in Taiwan, a Suez closure — propagates through the entire system within days.

8. Future I: AI & the Data Center Compute Cycle

To understand where chips are going, start with the constraint that increasingly dominates every conversation among hyperscaler CFOs: not GPU supply, but power. Training a frontier model in 2026 is no longer a chip problem. It is a substation problem.

8.1 NVIDIA's Roadmap: Blackwell, Rubin, and Beyond

NVIDIA's GPU roadmap moved to an annual cadence starting with the Hopper-Blackwell transition. Blackwell (B100/B200, GB200) ramped through 2024–2025. The Blackwell Ultra refresh hit volume in late 2025. Rubin, the next architecture, is scheduled for volume production through 2026 with shipments beginning to large customers by Q3, alongside the Vera CPU that complements it. Each generation roughly doubles training performance per dollar and per watt — but the absolute power draw per rack continues to climb. A Blackwell-class GB200 NVL72 rack consumes roughly 120 kW, several times more than legacy server racks.

8.2 Custom Silicon: The Hyperscaler Counterattack

Every major hyperscaler is now designing in-house AI silicon. Google's TPU has been in production for nearly a decade and now powers Gemini training and serving. Amazon's Trainium 2 reached mass production in 2025 with Trainium 3 sampling. Microsoft's Maia 100 entered production in 2024 with Maia 200 expected in 2026. Meta's MTIA chips are now used for ranking and recommendation. Apple is widely reported to be building its own AI server silicon for internal use.

The economics are compelling. A hyperscaler that spends $30 billion a year on NVIDIA GPUs can justify spending $1–2 billion designing its own. Even capturing 20–30% of the workload at 50% of NVIDIA's margin saves multiple billions per year. None of this dethrones NVIDIA in the next two years — but it changes the long-run trajectory of where the value flows in AI silicon.

8.3 The Power Wall

The constraint that may matter most by 2027 is electricity. AI data centers are now expected to consume 8–12% of US electricity by 2028 (up from 4–5% in 2023). The new capacity is concentrated in regions whose grids were not built for it: Northern Virginia, Texas, Arizona, Ohio. Hyperscalers are signing power purchase agreements for nuclear (Three Mile Island restart for Microsoft, Vogtle for Amazon, SMR commitments from Google and Amazon), gas, and renewables — sometimes years ahead of their data centers being built. In some regions, the gating factor for AI buildout is no longer the chip. It is the substation.

9. Future II: Chips in Space

The most underappreciated frontier in semiconductors is not on the ground. It is in low Earth orbit. Three independent trends — radiation-hardened silicon, the collapsing cost of launch, and the power constraint on terrestrial AI — are now converging on a thesis that would have been treated as science fiction five years ago: that some of the next decade's data centers will not be in Virginia or Texas, but in orbit.

9.1 Why Chips In Space Are Different

The hostile environment of space — high-energy particles, total ionizing dose, single-event upsets, extreme thermal cycling — destroys ordinary chips. For decades, the “rad-hard” semiconductor industry has been a small, defense-led niche making specialized chips a generation or two behind commercial silicon. Companies like Microchip (formerly Atmel's rad-hard line), BAE Systems, Honeywell, Cobham (now part of Frontgrade), and Vorago Technologies have served military, intelligence, and deep-space customers.

The new wave is different. Modern commercial constellations like Starlink ride on radiation-tolerant — not radiation-hardened — silicon, using software techniques (triple modular redundancy, error correction, scheduled reboots) to recover from upsets. This allows operators to use much closer-to-leading-edge chips, dramatically improving cost and capability. The same approach is now being applied to GPUs.

9.2 SpaceX: Starlink, Starshield, and Compute in Orbit

SpaceX is no longer just a launch company. It is, increasingly, the world's largest operator of orbital silicon. Starlink — with more than 6,000 active satellites in 2026 and approval to grow toward 12,000 — runs custom payload silicon for inter-satellite laser links, beam-forming phased arrays, and modem stacks. Each satellite is, in effect, a small flying datacenter node.

The Starshield program (the government-services variant of Starlink) is rumored to host considerably more sensitive payloads, including imaging, signals intelligence, and AI-accelerated edge processing. Reports of contracts with the US National Reconnaissance Office point to a constellation of hundreds of satellites with onboard compute for real-time imagery interpretation — exactly the workload modern AI inference excels at, and exactly the workload that until recently required downlinking data to ground stations.

Combine all of this with the dramatic fall in launch costs — Starship, when operational at full cadence, could deliver mass to orbit at $100/kg or less, versus $1,500/kg for Falcon 9 — and the unit economics of putting compute in orbit shift from impossible to interesting.

9.3 NVIDIA in Orbit

NVIDIA itself has begun showing up in space hardware. Various Earth-observation operators (Planet, Capella, BlackSky), defense primes, and at least one startup focused on orbital inference have begun deploying versions of NVIDIA's Jetson edge platform — the same line used for autonomous vehicles and robots — into satellite payloads. The pitch: terabits of raw imagery generated in orbit, but only the small fraction that matters needs to be downlinked. The rest is processed on-orbit by a GPU.

This is a meaningful inversion of the traditional satellite model. For 60 years, satellites were “dumb” — they captured signals and sent them home. Modern AI-capable satellites are the opposite: they capture far more than the downlink budget can carry, and use on-orbit inference to decide what is worth sending. This dramatically increases the value extracted per dollar of orbital capacity.

9.4 Google's Project Suncatcher: Orbital Data Centers

Among the “moonshot” programs at Google's parent Alphabet, one of the most striking is the early-stage research effort sometimes referred to as Project Suncatcher — a study of solar-powered data centers in low Earth orbit, networked by laser links, using TPUs (Google's in-house AI accelerator) as the compute substrate. The thesis is straightforward: in LEO, you can run TPUs on continuous solar power without the grid constraints, water constraints, or zoning constraints that bottleneck terrestrial buildouts. Cooling becomes a radiator problem rather than a chiller problem. Power is essentially unlimited.

This remains, by all available evidence, a research program rather than a deployment plan — and there are many unsolved problems (radiation, thermal management of dense compute, replacement and servicing, latency for non-AI workloads). But the conceptual leap matters. If even one hyperscaler commits to even a small-scale orbital test cluster within this decade, it changes the structural conversation about where compute is built.

9.5 What Could Go Wrong

The orbital compute thesis has real failure modes. The Kessler syndrome — a cascading-debris scenario where collisions in LEO render certain orbits unusable — is no longer theoretical; the 2009 Iridium-Cosmos collision and growing on-orbit congestion are warning signs. International regulation of orbital spectrum, debris liability, and dual-use payloads is far behind the pace of deployment. And the fundamental question of how you service or replace compute in orbit remains open. Most importantly, the cooling problem at scale is genuinely hard: dumping the heat from a megawatt-class compute cluster into space requires radiators on the scale of football fields.

10. Investment Implications & Risks

The semiconductor industry in 2026 offers the broadest opportunity set in the public equity markets — and the highest concentration of single-name geopolitical risk. Here is how to think about the landscape.

10.1 Picks and Shovels

ASML, TSMC, Applied Materials, LAM Research, KLA, and Tokyo Electron capture economics largely independent of which fabless winner emerges. They sell into every node, every architecture, every customer. They are the most direct expression of the structural thesis: more compute requires more wafers, more wafers require more equipment.

10.2 AI Beneficiaries

NVIDIA remains the dominant AI training name, though the second derivative (custom silicon penetration) is increasingly negative for its terminal margin assumptions. Broadcom has emerged as the leading designer of custom hyperscaler accelerators (Google TPU, Meta MTIA) and networking ASICs. AMD has captured a meaningful inference share with MI300/MI325/MI350. Marvell is a smaller but credible custom-silicon designer. SK Hynix, Samsung, and Micron are the leveraged plays on HBM demand.

10.3 Reshoring Beneficiaries

The build-out of TSMC Arizona, Intel Ohio, Samsung Texas, and TSMC Japan creates demand for a chain of US- and Japan-based suppliers: industrial gas providers (Linde, Air Products), construction primes (Bechtel, Fluor), specialty chemicals (Entegris, Versum/Merck Electronics), and US equipment names. The CHIPS Act subsidies are an unprecedented underwrite for this segment.

10.4 The Orbital Frontier

The pure-play orbital chip thesis is still mostly private (SpaceX is the dominant private name). Public expressions include defense primes with growing space portfolios (Lockheed Martin, Northrop Grumman, RTX, L3Harris), specialty satellite and ground-segment names (Iridium, Viasat, EchoStar, Rocket Lab), and the more speculative Earth-observation-with-AI names (Planet, BlackSky). NVIDIA's exposure here is real but small as a percentage of revenue.

10.5 The Tail Risks

Silicon is not a sector. It is the substrate of every other sector. Every dollar of AI capex, every gram of EV battery management, every megawatt of grid intelligence, every payload in low Earth orbit — runs through it. Understanding the stack, the chokepoints, and the geopolitics is no longer optional for a serious investor. It is the foundation of understanding the modern economy.